1. Field of the Invention
This invention relates to digital waveform synthesis. In particular, the invention relates to digital-to-time-domain conversion.
2. Description of Related Art
There are many factors affecting the operating frequency of digital circuits. These factors include environmental conditions (e.g., supply voltage and temperature) and electrical characteristics of the devices implementing the digital circuits. Among these factors, parasitic capacitance is a significant factor that may reduce the switching frequency.
In many applications, it is useful to synthesize digital waveforms according to some predefined pattern. It is desirable to be able to synthesize the digital waveforms at frequencies as high as possible. The digital-to-time-domain converter (DTC) is a basic building block used in digital waveform synthesis (DWS). The DTC performance is limited by the large parasitic capacitance that is inherently present on its output node. This parasitic capacitance places a limit on the highest frequency that can be synthesized using DWS.
Therefore, there is a need to have an efficient technique to reduce the output capacitance in the DTC.